P89LPC915FDH datasheet(11/75 Pages) NXP

11 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

11 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

7.2 Pin description

Table 4.

P89LPC915 pin description

Symbol

Type Description

P0.0 to P0.5

I/O

Port 0: Port 0 is a 6-bit I/O port with a user-conﬁgurable output type.

During reset Port 0 latches are conﬁgured in the input only mode with the

internal pull-up disabled. The operation of Port 0 pins as inputs and

outputs depends upon the port conﬁguration selected. Each port pin is

conﬁgured independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 15 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0/CMP2/KBI0

I/O

P0.0 — Port 0 bit 0.

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

P0.1/CIN2B/KBI1/AD10

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2/CIN2A/KBI2/AD11

I/O

P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1 analog input.

P0.3/CIN1B/KBI3/AD12

I/O

P0.3 — Port 0 bit 3.

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4/CIN1A/KBI4/AD13/

DAC1

I/O

P0.4 — Port 0 bit 4.

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD13 — ADC1 channel 3 analog input.

DAC1 — DAC1 analog output.

P0.5/CMPREF/KBI5/CLKIN

I/O

P0.5 — Port 0 bit 5.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

CLKIN — External clock input.

P1.0 to P1.5

I/O, I

[1]

Port 1: Port 1 is a 6-bit I/O port with a user-conﬁgurable output type,

except for three pins as noted below. During reset Port 1 latches are

conﬁgured in the input only mode with the internal pull-up disabled. The

operation of the conﬁgurable Port 1 pins as inputs and outputs depends

upon the port conﬁguration selected. Each of the conﬁgurable port pins

are programmed independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 15 “Static characteristics” for details. P1.2 to

P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P89LPC915FDH 데이터시트(PDF) 11 Page - NXP Semiconductors

P89LPC915FDH 데이터시트(HTML) 11 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

데이터시트 다운로드

링크 URL