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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCIMX258CJM4A 데이터시트(PDF) 56 Page - Freescale Semiconductor, Inc |
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PCIMX258CJM4A 데이터시트(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 144 page  i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3 56 Freescale Semiconductor 3.7.6 External Memory Interface (EMI) Timing The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash controller (NFC), and wireless external interface module (WEIM). The following subsections give timing information for these submodules. 3.7.6.1 ESDCTL Electrical Specifications 3.7.6.1.1 SDRAM Memory Controller The following diagrams and tables specify the timings related to the SDRAMC module which interfaces SDRAM. t4 CSPI SCLK transition time tpr 1 2.6 8.5 ns t5 SS n output pulse width tWsso 2Tsclk 2 +T wait 3 —— t5’ SS n input pulse width tWssi Tper 4 —— t6 SS n output asserted to first SCLK edge (SS output setup time) tSsso 3Tsclk —— t6’ SS n input asserted to first SCLK edge (SS input setup time) tSssi Tper —— t7 CSPI master: Last SCLK edge to SS n negated (SS output hold time) tHsso 2Tsclk —— t7’ CSPI slave: Last SCLK edge to SS n negated (SS input hold time) tHssi 30 — ns t8 CSPI master: CSPI1_RDY low to SS n asserted (CSPI1_RDY setup time) tSrdy 2Tper 5Tper — t9 CSPI master: SS n negated to CSPI1_RDY low tHrdy 0— ns t10 Output data setup time tSdatao (tclkoL or tclkoH or tclkiL or tclkiH) – Tipg 5 —— t11 Output data hold time tHdatao tclkoL or tclkoH or tclkiL or tclkiH —— t12 Input data setup time tSdatai Tipg + 0.5 — ns t13 Input data hold time tHdatai 0— ns t14 Pause between data word tpause 0— ns 1 The output SCLK transition time is tested with 25 pF drive. 2 T sclk = CSPI clock period 3 T wait = Wait time, as specified in the sample period control register 4 T per = CSPI reference baud rate clock period (PERCLK2) 5 T ipg = CSPI main clock IPG_CLOCK period Table 41. CSPI Interface Timing Parameters (continued) ID Parameter Description Symbol Minimum Maximum Units |
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