PCIMX258CJM4A datasheet(81/144 Pages) FREESCALE

81 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

Figure 53 shows the ESAI HCKR timing diagram.

Figure 53. ESAI HCKR Timing

Table 58 describes the general timing requirements for the ESAI module. Table 56 and Table 57 describe

respectively the conditions and signals cited in Table 58.

Table 56. ESAI Timing Conditions

Symbol

Significance

Comments

i ck

Internal clock

In the i.MX25, the internal clock frequency is equal to the IP bus frequency

(133 MHz)

x ck

External clock

The external clock may be derived from the CRM module or other external

clock sources

i ck a

Internal clock, asynchronous mode

In asynchronous mode, SCKT and SCKR are different clocks

i ck s

Internal clock, synchronous mode

In synchronous mode, SCKT and SCKR are the same clock

Table 57. ESAI Signals

Signal Name

Significance

SCKT

Transmit clock

SCKR

Receive clock

FST

Transmit frame sync

HCKT

Transmit high-frequency clock

HCKR

Receive high-frequency clock

Table 58. ESAI General Timing Requirements

No.

Characteristics1 2

Symbol

Expression3

Min.

Max.

Condition

Unit

Clock cycle4

tSSICC

× Tc

30.0

—

i ck

Clock high period

For internal clock

—

× Tc − 9.0

—

—ns

For external clock

—

× Tc

—

Clock low period

For internal clock

—2

× Tc − 9.0

—

—ns

For external clock

—

× Tc

—

HCKR

SCKR (output)

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