PCIMX258CJM4A datasheet(71/144 Pages) FREESCALE

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i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

Freescale Semiconductor

NOTE

The test condition load capacitance was 25 pF. Recommended drive

strength for all controls, address, and BCLK is maximum drive.

Recommended drive strength for all controls, address and BCLK is

maximum drive.

WE8

Clock rise/fall to RW_B valid

WE9

Clock rise/fall to RW_B invalid

WE10

Clock rise/fall to OE_B valid

WE11

Clock rise/fall to OE_B invalid

3.6

5.5

WE12

Clock rise/fall to EBy_B valid

11.5

WE13

Clock rise/fall to EBy_B invalid

WE14

Clock rise/fall to LBA_B valid

17.5

WE15

Clock rise/fall to LBA_B invalid

WE16

Clock rise/fall to output data valid

WE17

Clock rise to output data invalid

2.5

WE18

Input data valid to clock rise, FCE=1

—

WE19

Input data valid to clock rise, FCE=0

6.9

—

WE20

Clock rise to input data invalid, FCE=1

—

WE21

Clock rise to input data invalid, FCE=0

2.4

—

WE22

ECB_B setup time, FCE=1

—

WE23

ECB_B setup time, FCE=0

7.2

—

WE24

ECB_B hold time, FCE=1

—

WE25

ECB_B hold time, FCE=0

—

WE26

DTACK_B setup time

5.4

—

WE27

DTACK_B hold time

–3.2

—

1 High is defined as 80% of signal value; low is defined as 20% of signal value.

2 BCLK parameters are being measured from the 50% point. For example, high is defined as 50% of signal value and low is

defined as 50% as signal value.

Table 54. WEIM Bus Timing Parameters1 (continued)

Parameter

Min.

Max.

Unit

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