UJA1075TWSLASH5V0SLASHWD datasheet(21/53 Pages) NXP

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

21 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

Figure 7 illustrates how V1 and the PNP transistor combine to supply a slow ramping load

current of 250 mA with PDC = 0. Any additional load current requirement will be supplied

by the PNP transistor, up to its current limit. If the load current continues to rise, IV1 will

increase above the selected PDC threshold (to a maximum of 250 mA).

For a fast ramping load current, V1 will deliver the required load current (to a maximum of

250 mA) until the PNP transistor has switched on. Once the transistor has been activated,

V1 will deliver 85 mA (PDC = 0) with the transistor contributing the balance of the load

current (see Figure 8).

Fig 7.

V1 and PNP currents at a slow ramping load current of 250 mA (PDC = 0)

Fig 8.

V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0)

015aaa111

250 mA

85 mA

50 mA

load

current

215 mA

165 mA

PNP

current

IV1

Ith(act)PNP = 85 mA

(PDC = 0)

Ith(deact)PNP = 50 mA

(PDC = 0)

load

current

250 mA

−165 mA

0 mA

IV1

165 mA

250 mA

PNP

current

015aaa075

Ith(act)PNP = 85 mA

(PDC = 0)

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