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UJA1075TW/5V0/WD 데이터시트(PDF) 46 Page - NXP Semiconductors

부품명 UJA1075TW/5V0/WD
상세설명  High-speed CAN/LIN core system basis chip
PDF  53 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

UJA1075TW/5V0/WD 데이터시트(HTML) 46 Page - NXP Semiconductors

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UJA1075_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 May 2010
46 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
12. Package outline
Fig 20. Package outline SOT549-1 (HTSSOP32)
UNIT
A1
A2
A3
bp
cD(1)
E(2)
eHE
LLp
Z
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT549-1
03-04-07
05-11-02
w M
θ
A
A1
A2
Eh
Dh
D
L p
detail X
E
Z
exposed die pad side
e
c
L
X
(A3)
0.25
1
16
32
17
y
b
HE
0.95
0.85
0.30
0.19
Dh
5.1
4.9
Eh
3.6
3.4
0.20
0.09
11.1
10.9
6.2
6.0
8.3
7.9
0.65
1
0.2
0.78
0.48
0.1
0.75
0.50
p
v M A
A
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
A
max.
1.1
0
2.5
5 mm
scale
pin 1 index
MO-153



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