AD9961-EBZ datasheet(37/60 Pages) AD

37 / 60 page

AD9961/AD9963

Rev. 0 | Page 37 of 60

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NORMALIZED FREQUENCY (Relative to fDAC)

Figure 46. Pass-Band Response of the Rx Path Decimation Filter

The filter coefficients of the 2× decimation low-pass are shown

in Table 16.

Table 16.

Lower Coefficient

Upper Coefficient

Value

H(1)

H(43)

H(3)

H(41)

−32

H(5)

H(39)

H(7)

H(37)

−140

H(9)

H(35)

252

H(11)

H(33)

−422

H(13)

H(31)

682

H(15)

H(29)

−1086

H(17)

H(27)

1778

H(19)

H(25)

−3284

H(21)

H(23)

10364

H(22)

16384

ADC Digital Offset Adjustment

The Rx paths also have individual digital offsets that can be

applied to the data captured by the ADCs. The offset is a 6-bit

digital value that is added directly to the LSBs of the ADC

output data. The offset values are configured by first addressing

the ADC by setting the appropriate address in Register 0x05,

then writing the desired offset (in LSBs) into Register 0x10. For

example, to set offsets of +6 and −2 to the I and Q channels

respectively, the register write sequence is:

1. Write 0x01 into Register 0x05. This addresses the I channel

ADC.

2. Write 0x06 into Register 0x10. This sets the IADC_Offset

value to +6 LSBs.

3. Write 0x02 into Register 0x05. This addresses the Q

channel ADC.

4. Write 0xFE into Register 0x10. This sets the QADC_Offset

value to −2 LSBs.

5. Write 0x01 into Register 0xFF. This updates the data path

registers and applies the offset to the data.

6. Write 0x00 into Register 0x05. This returns the SPI to the

normal addressing mode.

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