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AD9961-EBZ 데이터시트(PDF) 53 Page - Analog Devices |
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AD9961-EBZ 데이터시트(HTML) 53 Page - Analog Devices |
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53 / 60 page ![]() AD9961/AD9963 Rev. 0 | Page 53 of 60 Digital Output Coding The digital output coding is straight binary. The ideal transfer characteristic for the auxiliary ADC is shown in Figure 86. 000 ... 000 000 ... 001 000 ... 010 111 ... 101 111 ... 110 111 ... 111 ANALOG INPUT +0.5 LSB 1 LSB +VFS – 1.5 LSB +VFS – 1 LSB Figure 86. Auxiliary ADC Transfer Function Auxiliary ADC Conversion Cycle A conversion is initiated by writing to SPI Register 0x77. The conversion starts on the first rising edge of the AUXADCCLK following a write to Register 0x77 (serial port register writes are completed on the eighth rising edge of SCLK during the data word write cycle). The conversion takes from 20 to 34 AUXADCCLK cycles to complete depending on the conversion time setting programmed in Register 0x77. In most cases, the ADC throughput is a function of both the serial port clock rate and the ADC conversion time. Figure 87 shows a typical timing scenario for an auxiliary ADC conversion period. The scenario shows the write that initiates the conversion, followed by the read that retrieves the conversion result. In some cases, it may be required to add a wait time between the write and read to ensure that the conversion is complete. The wait time depends on the ADC conversion cycle time and the speed of the serial port clock. The minimum wait time is calculated as: SCLK AUXADCCLK wait t t N t × − × + ≥ 7 ) 1 ( where N is the number of auxiliary ADC clock cycles that result from the conversion time setting in Register 0x7B. tSCLK is the serial port clock period. A negative wait time indicates no wait time is required. WRITE INSTR. WRITE INSTR. READ INSTR. DATA REG 0x77 ADC CONVERSION ADC CONVERSION SERIAL PORT WAIT WAIT DATA REG 0x78 DATA REG 0x77 DATA REG 0x79 AUX ADC CYCLE 1 AUX ADC CYCLE 2 Figure 87. Timing Scenario for Auxiliary ADC Conversion Cycle It should be noted that after initial power-up or recovery from power-down, the ADC needs about 100 µS to stabilize. In many cases, the results of the first conversion should be discarded in order for the auxiliary ADC to reach an optimum operating condition. AUXILIARY DACs The AD9963 has two 10-bit auxiliary DACs and two 12-bit auxiliary DACs suitable for calibration and control functions. The DACs have voltage outputs with selectable full-scale voltages and output ranges. The auxiliary DACs are configured and updated through the serial port interface. 10-Bit Auxiliary DACs The two 10-bit DACs have identical transfer functions and are output on the AUXIO2 and AUXIO3 pins. The two DACs can be independently enabled and configured. The DACs have five selectable top-of-scale voltages and four selectable output ranges, which result in 20 possible transfer functions. + – DACCODE[9:0] AVDD DAC10_RNG 0.5V 16k Ω AUXIO DAC10_RNG: 00 = 2.0V = 124µA Ifs 01 = 1.5V = 93µA Ifs 10 = 1.0V = 62µA Ifs 11 = 0.5V = 31µA Ifs RTOP DAC10_TOP: 000 = 1.0V = 16k Ω 001 = 1.5V = 8.0k Ω 010 = 2.0V = 5.3k Ω 011 = 2.5V = 4.0k Ω 100 = 3.0V = 3.2k Ω ISPAN Figure 88. Simplified Circuit Diagram of the 10-Bit Auxiliary DAC The circuit is most easily analyzed using superposition of two inputs to the op amp, the 0.5 V reference voltage, and the programmable current source. The following equation describes the no-load output voltage: × − × Ω + = SPAN TOP OUT I DACCODE R V V 1024 5. 0 k 16 5. 0 The DACCODE (see Register 0x49 and Register 0x4A for DAC10A and Register 0x46 and Register 0x47 for DAC10B) is interpreted such that ISPAN is full scale at 0x000 and zero at 0x3FF. This leads to an increasing output voltage with increasing code as shown in Figure 89 and Figure 90. The five selectable gain setting resistors of 3.2 kΩ, 4.0 kΩ, 5.3 kΩ, 8.0 kΩ, and 16 kΩ result in full-scale output voltage levels of 3.0 V, 2.5 V, 2.0 V, 1.5 V and 1.0 V respectively. The four selectable full-scale currents of 31 µA, 62 µA, 93 µA and 124 µA result in voltage output spans of 0.5 V, 1.0 V, 1.5 V, and 2.0 V, respectively. |
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