Clock operations

M48T129V, M48T129Y

12/28

Doc ID 5710 Rev 4

3

Clock operations

3.1

watchdog, interrupt, flag, and control data. These registers are memory locations which

contain external (user accessible) and internal copies of the data (usually referred to as

BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions

except that they are updated periodically by the simultaneous transfer of the incremented

3.2

Reading the clock

prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are

only data registers and not the actual clock counters, so updating the registers can be halted

without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h).

As long as a '1' remains in that position, updating is halted. After a halt is issued, the

registers reflect the count; that is, the day, date, and time that were current at the moment

simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second

after the READ bit is reset to a '0.'

3.3

Setting the clock

Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like

with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 13).

Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FFFFh-

resume. After the WRITE bit is reset, the next clock update will occur approximately one

second later.

Note:

Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset

to '0.'

3.4

Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant

amount of time on the shelf, the oscillator can be turned off to minimize current drain on the

battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the

oscillator. When reset to a '0', the M48T129Y/V oscillator starts within one second.

Note:

It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST

bit (FT) or the STOP bit (ST).