M48T129V, M48T129Y

Description

Doc ID 5710 Rev 4

5/28

1

Description

time clock with programmable alarms and a watchdog timer. The special DIP package

provides a fully integrated battery-backed memory and real-time clock solution. The

M48T129Y/V directly replaces industry standard 128 Kb x 8 SRAM. It also provides the non-

volatility of Flash without any requirement for special WRITE timing or limitations on the

number of WRITEs that can be performed.

The 32-pin, 600 mil DIP hybrid houses a controller chip, SRAM, quartz crystal, and a long-

life lithium button cell in a single package.

Figure 1.

Logic diagram

Table 1.

Signal names

A0-A16

Address inputs

DQ0-DQ7

Data Inputs / outputs

E

Chip enable input

G

Output enable input

W

WRITE enable input

RST

Reset output (open drain)

IRQ/FT

Interrupt / frequency test output (open drain)

Supply voltage

Ground

AI02260

17

A0-A16

DQ0-DQ7

VCC

M48T129Y

M48T129V

G

VSS

8

E

W

RST

IRQ/FT