MPC8572ECLPXATLD datasheet(31/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 7 and Figure 8 show the FIFO timing diagrams.

Figure 7. FIFO Transmit AC Timing Diagram

Rise time TX_CLK (20%–80%)

tFITR

—

0.75

Fall time TX_CLK (80%–20%)

tFITF

—

0.75

FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK

tFITDV

2.0

—

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time

tFITDX

0.5

—

3.0

Notes:

1. The minimum cycle period (or maximum frequency) of the TX_CLK is dependent on the maximum platform frequency of the

speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO

Restrictions,” for more detailed description.

Table 25. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period1

tFIR

5.3

8.0

100

RX_CLK duty cycle

tFIRH/tFIR

RX_CLK peak-to-peak jitter

tFIRJ

—

250

Rise time RX_CLK (20%–80%)

tFIRR

—

0.75

Fall time RX_CLK (80%–20%)

tFIRF

—

0.75

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tFIRDV

1.5

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tFIRDX

0.5

—

1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the

speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO

Restrictions,” for more detailed description.

Table 24. FIFO Mode Transmit AC Timing Specification (continued)

At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

tFIT

tFITH

tFITF

tFITDX

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

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