MPC8572ECLPXATLD datasheet(97/140 Pages) FREESCALE

97 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Serial RapidIO

Figure 59. Single Frequency Sinusoidal Jitter Limits

Table 73. Receiver AC Timing Specifications—3.125 GBaud

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Differential Input Voltage

VIN

200

1600

mV p-p

Measured at receiver

Deterministic Jitter Tolerance

0.37

—

UI p-p

Measured at receiver

Combined Deterministic and Random

Jitter Tolerance

JDR

0.55

—

UI p-p

Measured at receiver

Total Jitter Tolerance1

0.65

—

UI p-p

Measured at receiver

Multiple Input Skew

SMI

—

Skew at the receiver input

between lanes of a multilane

link

Bit Error Rate

BER

—

10-12

——

Unit Interval

320

+/- 100 ppm

Note:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 59. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

8.5 UI p-p

0.10 UI p-p

Sinusoidal

Jitter

Amplitude

22.1 kHz

1.875 MHz

20 MHz

Frequency

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