MPC8572ECLPXATLD datasheet(86/140 Pages) FREESCALE

부품명	MPC8572ECLPXATLD

상세설명	MPC8572E PowerQUICC III Integrated Processor Hardware Specifications

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

PCI Express

Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications

16.4.3

Differential Receiver (RX) Input Specifications

Table 62 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 62. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nominal

Max

Units

Comments

Unit Interval

399.88

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not

account for Spread Spectrum Clock

dictated variations. See Note 1.

VRX-DIFFp-p

Differential Input

Peak-to-Peak

Voltage

0.175

—

1.200

VRX-DIFFp-p = 2*|VRX-D+ - VRX-D-|

See Note 2.

TRX-EYE

Minimum

Receiver Eye

Width

0.4

—

The maximum interconnect media and

Transmitter jitter that can be tolerated by the

Receiver can be derived as TRX-MAX-JITTER

= 1 - TRX-EYE= 0.6 UI.

See Notes 2 and 3.

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