MPC8572ECLPXATLD datasheet(65/140 Pages) FREESCALE

65 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Programmable Interrupt Controller

11 Programmable Interrupt Controller

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed

polarity), it must remain asserted for at least 3 system clocks (SYSCLK periods).

12 JTAG

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the

MPC8572E.

Table 52 provides the JTAG AC timing specifications as defined in Figure 37 through Figure 39.

Table 52. JTAG AC Timing Specifications (Independent of SYSCLK) 1

At recommended operating conditions with OVDD of 3.3 V ± 5%.

Parameter

Symbol 2

Min

Max

Unit

Notes

JTAG external clock frequency of operation

fJTG

33.3

MHz

—

JTAG external clock cycle time

t JTG

—

JTAG external clock pulse width measured at 1.4 V

tJTKHKL

—

JTAG external clock rise and fall times

tJTGR & tJTGF

TRST assert time

tTRST

—

Input setup times:

Boundary-scan data

TMS, TDI

tJTDVKH

tJTIVKH

—

Input hold times:

Boundary-scan data

TMS, TDI

tJTDXKH

tJTIXKH

—

Valid times:

Boundary-scan data

TDO

tJTKLDV

tJTKLOV

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

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