MPC8572ECLPXATLD datasheet(47/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

8.3.4

SGMII AC Timing Specifications

This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver

characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver

inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 25, respectively.

8.3.4.1

SGMII Transmit AC Timing Specifications

Table 39 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.

8.3.4.2

SGMII Receive AC Timing Specifications

Table 40 provides the SGMII receive AC timing specifications. Source synchronous clocking is not

supported. Clock is recovered from the data. Figure 24 shows the SGMII receiver input compliance mask

eye diagram.

Table 39. SGMII Transmit AC Timing Specifications

At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic Jitter

—

0.17

UI p-p

—

Total Jitter

—

0.35

UI p-p

—

Unit Interval

799.92

800

800.08

VOD fall time (80%-20%)

tfall

—

120

—

VOD rise time (20%-80%)

trise

—

120

—

Notes:

1. Each UI is 800 ps ± 100 ppm.

Table 40. SGMII Receive AC Timing Specifications

At recommended operating conditions with XVDD_SRDS2 = 1.1V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic Jitter Tolerance

0.37

—

UI p-p

Combined Deterministic and Random Jitter Tolerance

JDR

0.55

—

UI p-p

Sinusoidal Jitter Tolerance

JSIN

0.1

—

UI p-p

Total Jitter Tolerance

0.65

—

UI p-p

Bit Error Ratio

BER

—

10-12

——

Unit Interval

799.92

800

800.08

AC Coupling Capacitor

CTX

—

200

Notes:

1. Measured at receiver.

2. Each UI is 800 ps ± 100 ppm.

3. The external AC coupling capacitor is required. It is recommended to be placed near the device transmitter outputs.

4. Refer to RapidIO™ 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications.

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