MPC8572ECLPXATLD datasheet(120/140 Pages) FREESCALE

120 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

120

Freescale Semiconductor

Clocking

Table 79 describes the clock ratio between e500 Core0 and the e500 core complex bus (CCB). This ratio

is determined by the binary value of LBCTL, LALE and LGPL2/LOE/LFRE at power up, as shown in

Table 79.

Table 80 describes the clock ratio between e500 Core1 and the e500 core complex bus (CCB). This ratio

is determined by the binary value of LWE[0]/LBS[0]/LFWE, UART_SOUT[1], and READY_P1 signals

at power up, as shown in Table 80.

19.4

DDR/DDRCLK PLL Ratio

The dual DDR memory controller complexes can be synchronous with, or asynchronous to, the CCB,

depending on configuration.

Table 81 describes the clock ratio between the DDR memory controller complexes and the DDR PLL

reference clock, DDRCLK, which is not the memory bus clock. The DDR memory controller complexes

clock frequency is equal to the DDR data rate.

When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default

mode of operation is for the DDR data rate for both DDR controllers to be equal to the CCB clock rate in

synchronous mode, or the resulting DDR PLL rate in asynchronous mode.

In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 81 reflects the DDR data rate

to DDRCLK ratio, because the DDR PLL rate in asynchronous mode means the DDR data rate resulting

from DDR PLL output.

Table 79. e500 Core0 to CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2/LOE/LFRE

Signals

e500 Core0:CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2/LOE/LFRE

Signals

e500 Core0:CCB Clock Ratio

000

Reserved

100

2:1

001

Reserved

101

5:2 (2.5:1)

010

Reserved

110

3:1

011

3:2 (1.5:1)

111

7:2 (3.5:1)

Table 80. e500 Core1 to CCB Clock Ratio

Binary Value of

LWE[0]/LBS[0]/

LFWE, UART_SOUT[1],

READY_P1 Signals

e500 Core1:CCB Clock Ratio

Binary Value of

LWE[0]/LBS[0]/

LFWE, UART_SOUT[1],

READY_P1 Signals

e500 Core1:CCB Clock Ratio

000

Reserved

100

2:1

001

Reserved

101

5:2 (2.5:1)

010

Reserved

110

3:1

011

3:2 (1.5:1)

111

7:2 (3.5:1)

MPC8572ECLPXATLD 데이터시트(PDF) 120 Page - Freescale Semiconductor, Inc

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