MPC8306EC datasheet(64/76 Pages) FREESCALE

부품명	MPC8306EC

상세설명	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

PDF	76 Pages

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

NOTE

Core VCO frequency = core frequency

 VCO divider. The VCO divider

(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO

frequency is in the range of 400–800 MHz.

22.4

QUICC Engine PLL Configuration

The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 58

shows the multiplication factor encodings for the QUICC Engine PLL.

0001

1:1

8

0001

1:1

8

0001

1.5:1

 2

0001

1.5:1

 4

0001

1.5:1

 8

0001

1.5:1

 8

0010

2:1

 2

0010

2:1

 4

0010

2:1

 8

0010

2:1

 8

0010

2.5:1

 2

0010

2.5:1

 4

0010

2.5:1

 8

0010

2.5:1

 8

0011

3:1

 2

0011

3:1

 4

0011

3:1

 8

0011

3:1

 8

Table 58. QUICC Engine PLL Multiplication Factors

RCWL[CEPMF]

RCWL[CEPDF]

QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF)

00000–00001

Reserved

00010

 2

00011

 3

00100

 4

Table 57. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

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