ACS411CS datasheet(14/43 Pages) SEMTECH

14 / 43 page

ACS411CS PRE-RELEASE Issue 6.0 July 1999.

uP Interface timing - MULTIPLEXED mode

In MULTIPLEXED mode, the device is configured to

interface with a microprocessor using a multiplexed

address/data bus. The following figures show the

timing diagrams of write and read accesses for this

mode.

The RDY low time Trdy is at least 2 CLKX cycles

after WRB/RDB going low.

Figure 4: Read access timing in MULTIPLEXED Mode.

address

RDY

CSB

RDB

WRB

data

ALE

tsu1

tsu2

td1

td2

td3

td4

td5

tpw2

tpw1

tpw3

th1

th2

th3

tp1

Symbol

Parameter

Min

Typ

Max

tsu1

Setup AD address valid to ALE

↓

5 *

tsu2

Setup CSB

↓ to RDB ↓

td1

Delay RDB

↓ to AD data valid

10 *

td2

Delay CSB

↓ to RDY active

10 *

td3

Delay RDB

↓ to RDY ↓

10 *

td4

Delay RDB

↑ to AD data High-Z

10 *

td5

Delay CSB

↑ to RDY High-Z

10 *

tpw1

RDB low time

tpw2

RDY low time

tpw3

ALE high time

10 *

th1

Hold AD address valid after ALE

↓

5 *

th2

Hold CSB low after RDB

↑

th3

Hold RDB low after RDY

↑

tp1

Time between ALE

↓ and RDB ↓

0 *

tp2

Time between consecutive accesses

(RDB

↑ to ALE ↑)

Note: preliminary timing information. Timing values marked with * TBA.

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