ACS411CS datasheet(16/43 Pages) SEMTECH

16 / 43 page

ACS411CS PRE-RELEASE Issue 6.0 July 1999.

uP Interface timing - INTEL mode

In INTEL mode, the device is configured to interface

with a microprocessor using a 80x86 type bus. The

following figures show the timing diagrams of write

and read accesses for this mode.

The RDY low time Trdy is at least 2 CLKX cycles

after WRB/RDB going low.

Figure 6: Read access timing in INTEL Mode.

Note: preliminary timing information. Timing values marked with * TBA.

RDY

CSB

RDB

WRB

data

address

tsu1

tsu2

td1

td2

td3

tpw2

tpw1

td4

td5

th1

th2

th3

Symbol

Parameter

Min

Typ

Max

tsu1

Setup A valid to CSB

↓

tsu2

Setup CSB

↓ to RDB ↓

td1

Delay RDB

↓ to AD valid

10 *

td2

Delay CSB

↓ to RDY active

10 *

td3

Delay RDB

↓ to RDY ↓

10 *

td4

Delay RDB

↑ to AD High-Z

10 *

td5

Delay CSB

↑ to RDY High-Z

10 *

tpw1

RDB low time

tpw2

RDY low time

th1

Hold A valid after RDB

↑

th2

Hold CSB low after RDB

↑

th3

Hold RDB low after RDY

↑

Time between consecutive accesses

(RDB

↑ to RDB ↓ or RDB ↑ to

WRB

↓)

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