ACS411CS datasheet(18/43 Pages) SEMTECH

18 / 43 page

ACS411CS PRE-RELEASE Issue 6.0 July 1999.

uP Interface timing - MOTOROLA mode

In MOTOROLA mode, the device is configured to

interface with a microprocessor using a 680x0 type

bus. The following figures show the timing diagrams

of write and read accesses for this mode.

The Dtack high time Trdy is at least 2 CLKX cycles

after CSB going low.

Figure 8: Read access timing in MOTOROLA Mode.

Note: preliminary timing information. Timing values marked with * TBA.

CSB

WRB

data

address

RDY

(DTACK)

tsu1

tsu2

td1

td2

td3

td4

tpw1

tpw2

th1

th2

th3

Symbol

Parameter

Min

Typ

Max

tsu1

Setup A valid to CSB

↓

tsu2

Setup WRB valid to CSB

↓

5 *

td1

Delay CSB

↓ to AD valid

10 *

td2

Delay CSB

↓ to DTACK ↑

10 *

td3

Delay CSB

↑ to AD High-Z

10 *

td4

Delay CSB

↑ to RDY High-Z

10 *

tpw1

CSB low time

tpw2

DTACK high time

th1

Hold A valid after CSB

↑

th2

Hold WRB high after CSB

↑

5 *

th3

Hold CSB low after DTACK

↓

Time between consecutive accesses

(CSB

↑ to CSB ↓)

ACS411CS 데이터시트(PDF) 18 Page - Semtech Corporation

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