MPC5125 datasheet(36/94 Pages) FREESCALE

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MPC5125 Microcontroller Data Sheet, Rev. 4

Pin Assignments

Freescale Semiconductor

3.2.1

Power and Ground Supply Summary

NOTE

This table indicates only the pins with a permanently enabled internal pullup, pulldown, or

Schmitt trigger. Most digital I/O pins can be configured to enable internal pullup, pulldown,

or Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), “I/O Control”

chapter.

Table 3. MPC5125 324 TEPBGA Power/Ground

Pin Name

Function Description

Voltage1

NOTES:

1 Nominal voltages.

Package Pin Locations

VDD

Supply voltage — e300 core and peripheral logic

1.4 V

J10, J11, J12, J13, K14, L9, L14, M9,

M14, N14, P10, P11, P12, P13

VDD_IO

Supply voltage — I/O buffers

3.3 V

A14, B9, B12, B17, C5, C14, D3, F2,

G4, H2, M2, R3, V3, W5, W15, AA4,

AA9, AA12, AA14, AA16, AB18

VDD_IO_MEM

Supply voltage — memory

—2

2 Dependent on external memory type. See Table 3

B19, C21, D17, D19, G19, H21, P19,

R21, T19, V19, W19, Y21, AB20

AVDD_FUSEWR

Power

3.3 V

AVDD_CPLL

Analog power

3.3 V

D10

AVDD_SPLL

Analog power

3.3 V

A11

AVDD_OSC_TMPS

Analog power

3.3 V

C10

VBAT

Power

3.3 V

AVSS_CPLL

Analog ground

0 V

B11

AVSS_OSC_TMPS_SPLL Analog ground—Double-bonded AVSS_OSC_TMPS

and AVSS_SPLL

0 V

B10

MVREF

Analog input —Voltage reference for SSTL input pads

—2

N19

MVTT0

Analog input —SSTL(DDR2) termination (ODT)

voltage

—2

W18

MVTT1

Analog input —SSTL(DDR2) termination (ODT)

voltage

—2

R19

MVTT2

Analog input —SSTL(DDR2) termination (ODT)

voltage

—2

M19

MVTT3

Analog input —SSTL(DDR2) termination (ODT)

voltage

—2

K19

VSS

Ground

0 V

A1, A2, A22, B1, B7, D7, D12, F4, F21,

J9, J14, K2, K[9:13], K21, L4, L[10:13],

L19, M[10:13], N[9:13], N21, P2, P4,

P9, P14, U2, U21, W8, W10, W12,

W17, Y2, AA6, AA18, AB1, AB22

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