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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADP1046ACPZ-R7 데이터시트(PDF) 91 Page - Analog Devices |
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ADP1046ACPZ-R7 데이터시트(HTML) 91 Page - Analog Devices |
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91 / 96 page  Data Sheet ADP1046 Rev. 0 | Page 91 of 96 Table 162. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode Bits Bit Name R/W Description [7:0] Δt5 (rising edge dead time of OUTC) R/W This register sets Δt5, which is the difference between the rising edge of OUTC and the mid- point of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the rising edge of OUTC is trailing tB. When the value is from 0x80 to 0xFF, the rising edge of OUTC is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt5 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing … … … … … … … … … 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading … … … … … … … … … 1 1 1 1 1 1 1 1 5 ns leading Table 163. Register 0x4A—Burst Mode Operation in Resonant Mode Bits Bit Name R/W Description [7:6] Burst mode enable R/W These bits are used to enable or disable burst mode operation. Bit 7 Bit 6 Burst Mode 0 0 Disabled 0 1 Enabled for normal operation, but disabled during soft start 1 0 Disabled 1 1 Enabled for normal operation and during soft start [5:0] Burst mode offset R/W These bits, along with the highest switching frequency limit, determine the threshold value for enabling burst mode operation. For information about how to set this value, see the Light Load Operation (Burst Mode) section. During burst mode, the PWM frequency is the maximum frequency limit set in Register 0x46. Table 164. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode Bits Bit Name R/W Description [7:0] Δt6 (falling edge dead time of OUTC) R/W This register sets Δt6, which is the leading time of the falling edge of OUTC from the end of the switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt6 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 … … … … … … … … … 1 1 1 1 1 1 1 1 1275 Table 165. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode Bits Bit Name R/W Description [7:0] Δt7 (rising edge dead time of OUTD) R/W This register sets Δt7, which is the difference between the rising edge of OUTD and the mid- point of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the rising edge of OUTD is trailing tB. When the value is from 0x80 to 0xFF, the rising edge of OUTD is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt7 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing … … … … … … … … … 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading … … … … … … … … … 1 1 1 1 1 1 1 1 5 ns leading |
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