C6416 datasheet(51/134 Pages) TI1

51 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

SIGNAL

TYPE†

IPD/

‡

DESCRIPTION

NAME

NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1/

URADDR3§

McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive

address 3 pin (I)

CLKR1/

URADDR2§

AB7

I/O/Z

McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I)

CLKX1/

URADDR4§

T12

I/O/Z

McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I)

DR1/

UXADDR1§

V11

McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I)

DX1/

UXADDR4§

Y10

I/O/Z

McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I)

FSR1/

UXADDR2§

AA8

I/O/Z

McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I)

FSX1/

UXADDR3§

AA11

I/O/Z

McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I)

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

CLKS0

IPD

McBSP0 external clock source (as opposed to internal)

CLKR0

I/O/Z

IPD

McBSP0 receive clock

CLKX0

I/O/Z

IPD

McBSP0 transmit clock

DR0

IPU

McBSP0 receive data

DX0

O/Z

IPU

McBSP0 transmit data

FSR0

I/O/Z

IPD

McBSP0 receive frame sync

FSX0

I/O/Z

IPD

McBSP0 transmit frame sync

TIMER 2

TOUT2

O/Z

IPD

Timer 2 or general-purpose output

TINP2

IPD

Timer 2 or general-purpose input

TIMER 1

TOUT1

O/Z

IPD

Timer 1 or general-purpose output

TINP1

IPD

Timer 1 or general-purpose input

TIMER 0

TOUT0

O/Z

IPD

Timer 0 or general-purpose output

TINP0

IPD

Timer 0 or general-purpose input

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

Ω resistor should be used.)

§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions

for this device.

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