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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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C6416 데이터시트(PDF) 71 Page - Texas Instruments |
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C6416 데이터시트(HTML) 71 Page - Texas Instruments |
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71 / 134 page  SMJ320C6414, SMJ320C6415, SMJ320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SGUS050A − JANUARY 2004 − REVISED MARCH 2004 71 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 power-down mode logic Figure 8 shows the power-down mode logic on the C6414/C6415/C6416. PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET CLKOUT6 PD3 Internal Peripherals CLKOUT4 Clock and Dividers Distribution † External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. SMJ320C6414/15/16 Figure 8. Power-Down Mode Logic† triggering, wake-up, and effects The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 9 and described in Table 33. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189). |
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