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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA339BW 데이터시트(PDF) 71 Page - STMicroelectronics |
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STA339BW 데이터시트(HTML) 71 Page - STMicroelectronics |
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71 / 77 page  STA339BW Application Doc ID 15251 Rev 5 71/77 7 Application 7.1 Application scheme for power supplies Here in Figure 22 below is the typical application diagram for STA339BW showing the power supply decoupling. Particular care has to be taken with the layout of the PCB. In particular the 3.3 Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This helps to prevent unwanted oscillation in the digital part of the device due to the inductive tracks of the PCB. The same rule also applies to all the decoulpling capacitors in order to limit spikes on all the supplies. Figure 22. Application diagram 7.2 PLL filter It is recommended to use the above scheme and values for the PLL filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, remember that the greater is the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. |
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