STA339BW datasheet(38/77 Pages) STMICROELECTRONICS

38 / 77 page

STA339BW

38/77

Doc ID 15251 Rev 5

6.6

Configuration register F (addr 0x05)

6.6.1

Output configuration

Note:

To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

OCFG1

OCFG0

110

Table 44.

Output configuration

Bit

R/W

RST

Name

Description

R/W

OCFG0

Selects the output configuration

R/W

OCFG1

Table 45.

Output configuration engine selection

OCFG[1:0]

Output configuration

Config pin

2 channel (full-bridge) power, 2 channel data-out:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

LineOut1

→ 3A/3B

LineOut2

→ 4A/4B

Line Out Configuration determined by LOC register

2(Half-Bridge).1(Full-Bridge) On-Board Power:

→ 1A

Binary 0 °

→ 1B

Binary 90°

3A/3B

→ 2A/2B Binary 45°

1A/B

→ 3A/B

Binary 0°

2A/B

→ 4A/B

Binary 90°

2 Channel (Full-Bridge) Power, 1 Channel FFX:

1A/1B

→ 1A/1B

2A/2B

→ 2A/2B

3A/3B

→ 3A/3B

EAPDEXT and TWARNEXT Active

1 Channel Mono-Parallel:

→ 1A/1B

w/ C3BO 45°

→ 2A/2B

w/ C3BO 45°

1A/1B

→ 3A/3B

2A/2B

→ 4A/4B

STA339BW 데이터시트(PDF) 38 Page - STMicroelectronics

STA339BW 데이터시트(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

데이터시트 다운로드

링크 URL