STA339BW datasheet(44/77 Pages) STMICROELECTRONICS

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STA339BW

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Doc ID 15251 Rev 5

6.6.2

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

6.6.3

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

6.6.4

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

6.6.5

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

6.6.6

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

Table 46.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

2R/W

IDE

Setting of 1 enables the automatic invalid input

detect mute

Table 47.

Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Table 48.

LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 49.

Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Table 50.

IC power down

Bit

R/W

RST

Name

Description

7R/W

PWDN

0: IC power down low-power condition

1: IC normal operation

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