STA339BW datasheet(33/77 Pages) STMICROELECTRONICS

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STA339BW

Doc ID 15251 Rev 5

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6.3

Configuration register C (addr 0x02)

6.3.1

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

6.3.2

FFX compensating pulse size register

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

111

Table 23.

FFX power output mode

Bit

R/W

RST

Name

Description

0R/W

OM0

Selects configuration of FFX output.

1R/W

OM1

Table 24.

Output modes

OM[1,0]

Output stage mode

Drop compensation

Discrete output stage - tapered compensation

Full power mode

Variable drop compensation (CSZx bits)

Table 25.

FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

Table 26.

Compensating pulse size

CSZ[3:0]

Compensating pulse size

0000

0 ns (0 tick) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 tick) clock period compensating pulse size

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