STA369BWS datasheet(79/89 Pages) STMICROELECTRONICS

79 / 89 page

STA369BWS

Doc ID 16861 Rev 4

79/89

Power down delay selector (PNDLSL[2:0]) bits

As per register MISC1 (addr 0x4B) on page 76, the assertion of PWDN activates a counter

that, by default, after 13 million clock cycles, puts the power bridge in tristate mode

independently from the fade out time. Using these registers it is possible to program this

counter as per the table below.

Short-circuit check enable (SHEN) bit

This bit, when enabled, activates the short-circuit checks before any power bridge activation

(EAPD bit 0 -> 1). See Section 6.17 on page 73 for more details.

6.21

Global DRC after B2DRC (GDRC) bit (addr 0x4D, bit D0)

GDRC bit, when set, changes the architecture configuration of the dual band DRC. As a

consequence, the block diagram, illustrated by the Figure 19: B2DRC scheme on page 67,

becomes that shown in Figure 26 below.

Figure 26.

Global DRC after B2DRC

The final effect is a global DRC after the dual band DRC. This architecture aims to limit the

signal overshoot, generated by the different phases of the two processed data paths of the

B2DRC architecture, that could happen between the two bands.

Note:

If GDRC is enabled, C3VR[0] and C3VR[1] must be set to 0 (default values).

Table 89.

PNDLSL bits configuration

PNDLSL[2]

PNDLSL[1]

PNDLSL[0]

Fade-out time

000Default time (13 x 106 PLL clock cycles)

001Default time divided by 2

010Default time divided by 4

011Default time divided by 8

100Default time divided by 16

101Default time divided by 32

110Default time divided by 64

111Default time divided by 128

Pass

Filter

Pass

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter

CH3

Volume

Vol

And

Limiter

DRC2

CH3

Volume

Vol

And

Limiter

DRC2

CH1

Volume

Vol

And

Limiter

DRC1

CH2

Volume

Vol

And

Limiter

DRC1

Pass

Filter

Pass

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter

CH3

Volume

Vol

And

Limiter

DRC2

CH3

Volume

Vol

And

Limiter

DRC2

CH1

Volume

Vol

And

Limiter

DRC1

CH2

Volume

Vol

And

Limiter

DRC1

STA369BWS 데이터시트(PDF) 79 Page - STMicroelectronics

STA369BWS 데이터시트(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

데이터시트 다운로드

링크 URL