STA381BWS datasheet(93/171 Pages) STMICROELECTRONICS

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STA381BWS

Doc ID 018937 Rev 6

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Table 87.

PNDLSL bits configuration

6.30.6

Short-circuit check enable bit

This bit, when enabled, will activate the short-circuit checks before any power bridge

activation (EAPD bit 0->1). See section Section 6.28: Short-circuit protection mode registers

SHOK (address 0x58) for more details.

6.31

Bad PWM detection registers (address 0x5E, 0x5F, 0x60)

The STA381BWS implements a detection on PWM outputs able to verify if the output signal

has no zero-crossing in a configurable time window. This check can be useful to detect the

DC level in the PWM outputs. To be noted that the checks are performed on logic level PWM

(i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs).

In case of ternary modulation, the detection threshold is computed as:

TH=[(BPTH*2+1)/128]*100%

If the measured PWM duty cycle is detected greater than or equal to TH for more than

BPTIM PWM periods, the corresponding PWM bit will be set in register 0x01.

In case of binary modulation, there are two thresholds:

TH1=[(64+BPTH)/128]*100%

TH2=[(64-BPTH)/128]*100%

In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than

BPTIM PWM periods, the corresponding bit will be set in register 0x4E.

PNDLSL[2]

PNDLSL[1]

PNDLSL[2]

Fade-out time

Default time (13M PLL clock cycles)

Default time divided by 2

Default time divided by 4

Default time divided by 8

Default time divided by 16

Default time divided by 32

Default time divided by 64

Default time divided by 128

BPTH[5]

BPTH[4]

BPTH[3]

BPTH[2]

BPTH[1]

BPTH[0]

reserved

BPTIM[7]

BPTIM[6]

BPTIM[5]

BPTIM[4]

BPTIM[3]

BPTIM[2]

BPTIM[1]

BPTIM[0]

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