STA381BWS datasheet(149/171 Pages) STMICROELECTRONICS

149 / 171 page

STA381BWS

Doc ID 018937 Rev 6

149/171

7.20

Short-circuit protection mode registers SHOK (address 0x47)

The following power bridge pins short-circuit protections are implemented in the

STA381BWS:

●

OUTxx vs GNDx

●

OUTxx vs VCCx

●

OUT1B vs OUT2A

The protection is enabled when reg. 0x4C bit 0 (SHEN) is set to ‘1’. The protection will check

the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched

on), and only if the test passes (no short) does the power bridge leave the tristate condition.

GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on

VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is

shorted to OUT2A.

Table 167.

PLL register 0x45 bits

Bit

R/W

RST

Name

Description

R/W

PLL_DIRP

‘0’: PLL configuration is determined by MCS bits

‘1’: PLL configuration is determined by FRAC, IDIV

and NDIV

R/W

PLL_PWD

‘0’: PLL normal behavior

‘1’: PLL is in power-down mode

R/W

PLL_BYP

‘0’: sys clock is from PLL

‘1’: sys clock is from external pin (PLL is bypassed)

2R/W

OSC_PD

‘0’: Normal behavior

‘1’: Internal oscillator is in power-down

R/W

BOOST32K

‘0’: Input oversampling selected by IR bits

‘1’: Input oversampling is selected x3

Table 168.

PLL register 0x46 bits

Bit

R/W

RST

Name

Description

BYPSTATE

PLL bypass state

PDSTATE

PLL PD state

OSCOK

OSCI locked

LOWCK

Clock input frequency check

reserved

GNDSH

VCCSH

OUTSH

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