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ST10F280 데이터시트(PDF) 234 Page - STMicroelectronics |
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ST10F280 데이터시트(HTML) 234 Page - STMicroelectronics |
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234 / 239 page ![]() Electrical characteristics ST10F280 234/239 Doc ID 8673 Rev. 3 Figure 92. SSC slave timing 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. t 313 t 314 t 315 t 315 t 315 t 316 t i B t u O t s a L t i B t u O t s 12nd Out Bit t 310 t 312 t 311 1) 2) t 317 2nd.In Bit 1st.In Bit t 318 t 317 Last.In Bit t 318 SCLK MRST MTSR GAPGCFT00947 |
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