ST10F280_12 datasheet(232/239 Pages) STMICROELECTRONICS

232 / 239 page

Electrical characteristics

ST10F280

232/239

Doc ID 8673 Rev. 3

The formula for SSC Clock Cycle time is: t300 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned

16-bit integer.

Figure 91.

SSC master timing

The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

The bit timing is repeated for all bits to be transmitted or received.

t307p

Read data setup time

before latch edge, phase

error detection on

(SSCPEN = 1)

37.5

–

2 TCL +

12.5

–ns

t308p

Read data hold time after

latch edge, phase error

detection on (SSCPEN = 1)

–

4 TCL

–

t307

Read data setup time

before latch edge, phase

error detection off

(SSCPEN = 0)

–

2 TCL

–

t308

Read data hold time after

latch edge, phase error

detection off (SSCPEN = 0)

0–

–

Timing guaranteed by design.

Table 52.

SSC master timing (continued)

Symbol

Parameter

Maximum Baud rate =

10M Baud (<SSCBR> =

0001h)

Variable Baud rate

(<SSCBR>=0001h-

FFFFh)

Min.

Max.

Min.

Max.

303

304

305

306

2nd Out Bit

300

302

301

307

2nd.In Bit

1st.In Bit

308

307

Last.In Bit

308

SCLK

MTSR

MRST

GAPGCFT00946

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