ST10F280_12 datasheet(231/239 Pages) STMICROELECTRONICS

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ST10F280

Electrical characteristics

Doc ID 8673 Rev. 3

231/239

Figure 90.

External bus arbitration, (regaining the bus)

1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated

earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be

deactivated without the ST10F280 requesting the bus

The next ST10F280 driven bus cycle may start here.

20.4.14

High-speed synchronous serial interface (SSC) timing

Master mode

VCC = 5 V ±10%, VSS = 0 V, CPU clock = 40 MHz, TA = -40°C to 125°C, CL = 50 pF

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

GAPGCFT00944

Table 52.

SSC master timing

Symbol

Parameter

Maximum Baud rate =

10M Baud (<SSCBR> =

0001h)

Variable Baud rate

(<SSCBR>=0001h-

FFFFh)

Min.

Max.

Min.

Max.

t300

CC SSC clock cycle time

100

8 TCL

262144

TCL

t301

CC SSC clock high time

–

t300/2 - 10

–

t302

CC SSC clock low time

–

t300/2 - 10

–

t303

CC SSC clock rise time

–

t304

CC SSC clock fall time

–

t305

Write data valid after shift

edge

–

t306

Write data hold after shift

edge(1)

-2

–

-2

–

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