 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
SPEAR1310 데이터시트(PDF) 8 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPEAR1310 데이터시트(HTML) 8 Page - STMicroelectronics |
|
|
8 / 57 page  Description SPEAr1310 8/57 Doc ID 17528 Rev 4 Table 1 provides an overview of SPEAr1310 features and capabilities. Table 1. SPEAr1310 features and capabilities overview Category Feature Instances / Details Notes CPU subsystem Processor cores 2x Cortex A9@600 MHz 32+32 KB L1 per core Includes: – 1x 64-bit global timer – 2x 32-bit timers – 2x watchdog/timers L2 Cache 1x 512 KB ECC Debug & test 2x JTAG-PTM Interconnect Internal bus 1x 64 bit @ 166 MHz Network-on-chip Reset and clock RCG generator 1x Reset and clock generation module Configuration MISC 1x Miscellaneous SoC configuration registers Power management PCM 1x Power control module Memories BootROM 1x 32 KB On-chip ROM for boot firmware SRAM 2x 32 KB + 4 KB Static RAM MPMC 1x up to 1 GB DDR2: 400 MHz + ECC DDR3: 533 MHz + ECC DDR 2/3 controller FSMC 1x 16-/32-bit Parallel NAND/NOR Flash Parallel Flash controller SMI 1x 4x 16 MB C.S.@50Mbps Serial NOR Flash SPI Flash controller |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
