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SPEAR1310 데이터시트(PDF) 26 Page - STMicroelectronics

부품명 SPEAR1310
상세설명  Dual-core Cortex A9 embedded MPU for communications
PDF  57 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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SPEAR1310 데이터시트(HTML) 26 Page - STMicroelectronics

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PCI Express (PCIe)
SPEAr1310
26/57
Doc ID 17528 Rev 4
The features common to both EP and RC mode of the DM cores are:
●
Support for all non-optional features and some optional features defined in the PCI
Express Base 2.0 specification.
●
Ultra-low transmit and receive latency
●
Support a max payload size of 256 bytes
●
4-KB maximum request size
●
Very high accessible bandwidth
●
Support for both Gen1 (at 125 MHz) and Gen2 (at 250 MHz) operation
●
2.5 Gbps (Gen1) or 5.0 Gbps (gen2) Lane (x1)
●
Automatic Lane reversal as specified in the PCI Express 2.0 specification (transmit and
receive)
●
Polarity inversion on receive
●
Multiple virtual channels (VCs) (maximum of 2)
●
Multiple traffic classes (TCs)
●
Supports ECRC generation and checking
●
Supports PCI Express beacon and wake-up mechanism
●
Supports PCI power management
●
Supports PCI Express active state power management (ASPM)
●
Supports PCI Express advanced error reporting
●
Supports Vital product data (VPD)
●
Supports PCIe messages for both transmit and receive.
●
Supports external priority arbitration (in addition to the internally-implemented transmit
arbitration)
●
Supports expansion ROM
Additional features specific to RC mode
The features specific to the RC mode are:
●
Type 1 configuration space
●
Application-initiated Lane reversal for situations where the core does not detect Lane 0
(for example, an x4 core connected to an x8 device that has its Lanes reversed)
Additional features specific to EP mode
The features specific to the EP mode are:
●
Alternate routing-ID (ARI)
●
Address translation services (ATS)
●
Completion timeout ranges
●
Function level reset (FLR)
●
Type 0 configuration space
●
MSI interrupt capability



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