SPEAR1340 datasheet(151/200 Pages) STMICROELECTRONICS

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SPEAr1340

Timing characteristics

Doc ID 023063 Rev 4

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Timing characteristics

This chapter provides the timing characteristics for the synchronous and asynchronous IPs

present in SPEAr1340.

The timings have been calculated under the following operating conditions:

●

In worst case: V= 0.90 V, T = 125 °C

●

In best case: V= 1.10 V, T = 40 °C

In Table 58 you will find an explanation of the symbols used in this chapter to describe timing

parameters.

5.1

Reset timing characteristics

Note:

Warm reset can be triggered by software by writing any value to the miscellaneous register

SYS_SW_RES.

Table 58.

Symbol definition

Symbol

Definition

TCLK

Clock period: the time for a complete clock cycle.

TCLKhigh

High-pulse width: the minimum amount of time for the high pulse of the clock.

TCLKlow

Low-pulse width: the minimum amount of time for the low pulse of the clock.

Tsetup (Ts)

Setup time: the minimum amount of time the data signal should be held steady

before the clock event so that the data is reliably sampled.

Thold (Th)

Hold time: the minimum amount of time the data signal should be held steady

after the clock event so that the data is reliably sampled.

Clock-to-output delay: the maximum time required to obtain a valid output after

the clock edge.

Table 59.

Reset timing characteristics

Symbol

Description

Min

Unit

tRP(cold)

MRESETn pin active low state duration for cold

reset (startup time from all supplies up and

stable).

See Figure 14: Cold reset release on page 149)

2ms

tRP(warm)

MRESETn pin active low state duration for warm

reset (minimum pulse width able to reset the

device).

See Figure 15: Warm reset release on

page 149)

500

µs

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