SPEAR1340 datasheet(20/200 Pages) STMICROELECTRONICS

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Device functions

SPEAr1340

20/200

Doc ID 023063 Rev 4

Main features:

UART0 and UART1:

●

Support baud rate up to UARTCLK/16

●

Programmable baud rate generation (integer and fractional parts)

●

Support three options on the UARTCLK clock frequency:

–

48 MHz: maximum baud rate of 3 Mbps (48/16)

–

24 MHz: maximum baud rate of 1.5 Mbps (24/16)

–

Programmable by software: up to 125 MHz with a maximum baud rate of 7.81

Mbps (125/16).

●

Separate 16x8 transmit and 16x12 receive first-in, first-out memory buffers (FIFOs)

●

Programmable FIFO disabling for 1-byte depth

●

FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4 and 7/8

●

Independent masking of transmit FIFO, receive FIFO, receive time-out, and error

condition interrupts

●

Support for direct memory access (DMA)

●

False start bit detection

●

Line break generation and detection

●

Programmable usage of IrDA SIR encoder/decoder:

IrDA SIR ENDEC block provides:

–

Support of IrDA SIR ENDEC functions for data rates up to 115.2 Kbits/second

half-duplex

–

Support of normal 3/16 and low-power bit durations

–

Programmable internal clock generator enabling division of reference clock by 1 to

256 for low-power mode bit duration

●

Fully-programmable serial interface characteristics:

–

data can be 5, 6, 7, or 8 bits

–

even, odd, stick, or no-parity bit generation and detection

–

1 or 2 stop bit generation

UART0 only:

●

Programmable hardware flow control which uses the CTS input and the RTS output to

automatically control the serial data flow

●

Support modem status which uses:

–

Input signals: Clear To Send (CTS), Data Carrier Detect (DCD), Data Set Ready

(DSR), and Ring Indicator (RI)

–

Output modem control lines: Request To Send (RTS), and Data Terminal Ready

(DTR)

●

Independent masking of modem status

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