SPEAR1340 datasheet(34/200 Pages) STMICROELECTRONICS

34 / 200 page

Device functions

SPEAr1340

34/200

Doc ID 023063 Rev 4

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Single FIFO per channel for source and destination

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FIFO depth configured to 16 bytes for the first 4 channels and to 128 bytes for the last 4

channels

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D flip-flop-based FIFO

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Automatic data packing or unpacking to fit FIFO width

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Programmable source and destination for each channel

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Programmable transfer type for each channel (memory-to-memory, memory-to-

peripheral, peripheral-to-memory, and peripheral-to-peripheral)

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Programmable burst transaction size for each channel

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Programmable enable and disable of DMA channel

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Support for disabling channel without data loss

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Support for suspension of DMA operation

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Support for RETRY, SPLIT, and ERROR responses

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Programmable maximum burst transfer size per channel

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Maximum transaction size configured to 256 for all the channels

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Maximum block size configured to 4095 for all the channels

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Bus locking – can be programmed to be over the transaction, block, or DMA transfer

level

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Channel locking – can be programmed to be over the transaction, block, or DMA

transfer level

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16 handshaking interfaces for source and destination peripherals

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Hardware and software handshaking interfaces

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Peripheral interrupt handshaking interface

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Handshaking interface supports single or burst DMA transactions

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Polarity control for hardware handshaking interface

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Enabling and disabling of individual DMA handshaking interface

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Programmable flow control at block transfer level (source, destination or DMAC core)

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Software control of source data pre-fetch when destination is flow controller

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Combined and separate interrupt requests

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Interrupt generation on DMA transfer (multiblock) completion, block transfer

completion, single and burst transaction completion and error condition

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Support of interrupt enabling and masking.

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