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M24LR64E-R 데이터시트(PDF) 36 Page - STMicroelectronics

부품명 M24LR64E-R
상세설명  64-Kbit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz
PDF  140 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24LR64E-R 데이터시트(HTML) 36 Page - STMicroelectronics

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I2C device operation
M24LR64E-R
36/140
Doc ID 022712 Rev 3
Figure 10.
Write cycle polling flowchart using ACK
5.10
Minimizing system delays by polling on ACK
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is
shown in Table 123, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
1.
Initial condition: a write cycle is in progress.
2.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3.
Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus
master goes back to Step 1. If the device has terminated the internal write cycle, it
responds with an Ack, indicating that the device is ready to receive the second part of
the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send address
and receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES
NO
Start
condition
Continue the
Write operation
Continue the
Random Read operation



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