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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8980CGEFL/V 데이터시트(PDF) 106 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V 데이터시트(HTML) 106 Page - Wolfson Microelectronics plc |
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106 / 123 page  WM8980 Pre-Production w PP, Rev 3.8, May 2012 106 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3 NGEN 0 ALC Noise gate function enable 1 = enable 0 = disable Input Limiter/ Automatic Level Control (ALC) 2:0 NGTH 000 ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db … (6dB steps) 111=-81dB Input Limiter/ Automatic Level Control (ALC) 36 (24h) 8:5 0000 Reserved 4 PLL PRESCALE 0 Divide MCLK by 2 before input to PLL Master Clock and Phase Locked Loop (PLL) 3:0 PLLN[3:0] 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Master Clock and Phase Locked Loop (PLL) 37 (25h) 8:6 000 Reserved 5:0 PLLK[23:18] 01100 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 40 (28h) 8:2 000000 Reserved 4 QBOOST 0 Increases ‘Q’ of video filter Video Buffer 1 VBGAIN 0 Video buffer gain 0 = 0dB (=6dB unloaded) 1 = +6dB (=12dB unloaded) Video Buffer 0 VBCLAMPEN 0 Video buffer clamp enable 0 = disabled 1 = enabled Video Buffer 41 (29h) 8:4 00000 Reserved 3:0 DEPTH3D 0000 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) 3D Stereo Enhancement 43 (2Bh) 8:6 000 Reserved 5 MUTERPGA 2INV 0 Mute input to INVROUT2 mixer Analogue Outputs 4 INVROUT2 0 Invert ROUT2 Output Analogue Outputs |
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