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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8352 데이터시트(PDF) 34 Page - Wolfson Microelectronics plc |
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WM8352 데이터시트(HTML) 34 Page - Wolfson Microelectronics plc |
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34 / 336 page  WM8352 Production Data w PD, February 2011, Rev 4.4 34 10.4 AUDIO INTERFACE TIMING - TDM MODE In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8352 ADCDAT tri-stating at the start and end of the data transmission is described in Figure 17 and the table below. Figure 17 Digital Audio Data Timing - TDM Mode Test Conditions DBVDD = 3.3V, DGND = 0V, TA=+25 oC, Master Mode, fs=48kHz, 24-bit data, unless otherwise stated. PARAMETER CONDITIONS MIN TYP MAX UNIT Audio Data Timing Information ADCDAT setup time from BCLK falling edge DCVDD = 3.6V 5 ns DCVDD = 1.8V 15 ns ADCDAT release time from BCLK falling edge DCVDD = 3.6V 5 ns DCVDD = 1.8V 15 ns |
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