WM8352 datasheet(94/336 Pages) WOLFSON

94 / 336 page

WM8352

Production Data

PD, February 2011, Rev 4.4

Figure 54 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1)

13.10.2 AUDIO INTERFACE TDM MODE

The digital audio interface on WM8352 has the facility of tri-stating the ADCDAT pin to allow multiple

data sources to operate on the same bus. Time division multiplexing (TDM) is also supported,

allowing audio output data to be transferred simultaneously from two different sources.

TDM mode is enabled for the ADC and DAC by register bits AIFADC_TDM and AIFDAC_TDM

respectively. TDM slot selection for the WM8352 is set for the ADC and DAC by register bits

AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN respectively, as defined in Table 46. When not

actively transmitting data, the ADCDAT pin will be tristated in TDM mode, to allow other devices to

transmit data.

13.10.3 TDM DATA FORMATS

All selectable data formats support TDM. The allocation of time slots is controlled by register bits

AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. Two possible slots (SLOT0 and SLOT1) are

available for the ADC and for the DAC.

Timing signals for the various interface formats in TDM mode are shown below for the ADC. Similar

slot allocation will exist for the DAC.

Left Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles

from the start of SLOT0 to the start of SLOT1 is determined by the selected word length of the

interface of the WM8352.

Figure 55 Left Justified Mode with TDM

Right Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles

from the end of SLOT1 to the end of SLOT0 is determined by the selected word length of the

interface of the WM8352.

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