WM8352 datasheet(199/336 Pages) WOLFSON | Wolfson AudioPlus™ Stereo CODEC with Power Management

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WM8352 데이터시트(PDF) 199 Page - Wolfson Microelectronics plc

부품명	WM8352

상세설명	Wolfson AudioPlus™ Stereo CODEC with Power Management

PDF	336 Pages

Scroll/Zoom	100%

제조업체	WOLFSON [Wolfson Microelectronics plc]

홈페이지	http://www.wolfsonmicro.com

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Production Data

WM8352

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PD, February 2011, Rev 4.4

199

24.2 FIRST-LEVEL INTERRUPTS

Each first level interrupt has a status bit in Register R24, which can be read to determine the origin of

an IRQ event.

Each of these bits may be masked by setting the corresponding field in Register R32. By default, the

first-level interrupts are all masked.

ADDRESS

BIT

LABEL

DESCRIPTION

R24 (18h)

System

Interrupts

13

OC_INT

First-level over-current interrupt.

Note: This bit is cleared once read.

12

UV_INT

First-level under-voltage interrupt.

Note: This bit is cleared once read.

9

CS_INT

First-level current sink interrupt.

Note: This bit is cleared once read.

8

EXT_INT

First-level external interrupt.

Note: This bit is cleared once read.

7

CODEC_INT

First-level codec interrupt.

Note: This bit is cleared once read.

6

GP_INT

First-level GPIO interrupt.

Note: This bit is cleared once read.

5

AUXADC_INT

First-level AUXADC comparator interrupt.

Note: This bit is cleared once read.

4

RTC_INT

First-level RTC interrupt.

Note: This bit is cleared once read.

3

SYS_INT

First-level system interrupt.

Note: This bit is cleared once read.

2

CHG_INT

First-level charger interrupt.

Note: This bit is cleared once read.

1

USB_INT

First-level USB interrupt.

Note: This bit is cleared once read.

0

WKUP_INT

First-level wakeup interrupt.

Note: This bit is cleared once read.

R32 (20h)

System

Interrupt Mask

13:0

“IM_” + name of respective

bit in R25

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R32 enables or masks the

corresponding bit in R24.

The default value for these bits is 1

(masked)

Note: Register is R24 is read-only.

Table 142 First Level Interrupt Status and Mask Bits

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