WM8352 datasheet(204/336 Pages) WOLFSON

204 / 336 page

WM8352

Production Data

PD, February 2011, Rev 4.4

204

24.3.7

AUXADC AND DIGITAL COMPARATOR INTERRUPTS

The first-level AUXADC_INT interrupt comprises several second-level interrupts for the auxiliary ADC

and associated digital comparators. Each of these has a status bit in Register R26 and a mask bit in

ADDRESS

BIT

LABEL

DESCRIPTION

R26 (1Ah)

Interrupt

Status 2

AUXADC_DATARDY_EINT

Auxiliary data ready.

(Rising Edge triggered)

Note: This bit is cleared once read.

AUXADC_DCOMP4_EINT

DCOMP4 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

AUXADC_DCOMP3_EINT

DCOMP3 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

AUXADC_DCOMP2_EINT

DCOMP2 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

AUXADC_DCOMP1_EINT

DCOMP1 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

R34 (22h)

Interrupt

Status 2 Mask

8:4

“IM_” + name of respective

bit in R26

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R34 enables or masks the

corresponding bit in R26. The default

value for these bits is 0 (unmasked).

Table 149 AUXADC Interrupts

24.3.8

RTC INTERRUPTS

The first-level RTC_INT interrupt comprises three second-level interrupts for the Real Time Clock.

Each of these has a status bit in Register R25 and a mask bit in Register R33, as defined in Table

150.

ADDRESS

BIT

LABEL

DESCRIPTION

R25 (19h)

Interrupt Status

RTC_PER_EINT

RTC periodic interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

RTC_SEC_EINT

RTC 1s rollover complete (1Hz tick).

(Rising Edge triggered)

Note: This bit is cleared once read.

RTC_ALM_EINT

RTC alarm signalled.

(Rising Edge triggered)

Note: This bit is cleared once read.

R33 (21h)

Interrupt Status

1 Mask

7:5

“IM_” + name of respective

bit in R25

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R33 enables or masks the

corresponding bit in R25. The default

value for these bits is 0 (unmasked).

Table 150 RTC Interrupts

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