전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

WM8953ECS/RV 데이터시트(PDF) 64 Page - Wolfson Microelectronics plc

부품명 WM8953ECS/RV
상세설명  Low Power Stereo ADC with PLL and TDM Interface
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8953ECS/RV 데이터시트(HTML) 64 Page - Wolfson Microelectronics plc

Back Button WM8953ECS/RV Datasheet HTML 60Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 61Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 62Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 63Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 64Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 65Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 66Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 67Page - Wolfson Microelectronics plc WM8953ECS/RV Datasheet HTML 68Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 64 / 100 page
background image
WM8953
Production Data
w
PD, January 2009, Rev 4.0
64
MASTER MODE BCLK AND ADCLRC ENABLE
The audio interface pins BCLK, ADCLRC and ADCDAT can be independently programmed to
operate in master mode or slave mode using register bit AIF_MSTR.
When the audio interface is operating in slave mode, the BCLK and ADCLRC clock outputs to these
pins are by default disabled to allow the digital audio source to drive these pins.
It is also possible to force the ADCLRC to be output using register bit ADCLRC_DIR, allowing mixed
master and slave mode.
The clock generators for the audio interface are enabled according to the control signals shown in
Figure 47.
Figure 47 Clock Output Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
15
AIF_MSTR
0b
Audio Interface Master Mode Select
0 = Slave mode
1 = Master mode
11
ADCLRC_DIR
0b
ADCLRC Direction
(Forces ADCLRC clock to be output in
slave mode)
0 = ADCLRC normal operation
1 = ADCLRC clock output enabled
R8 (08h)
10:0
ADCLRC_RATE
[10:0]
040h
ADCLRC Rate
ADCLRC clock output = BCLK /
ADCLRC_RATE
Integer (LSB = 1)
Valid from 8..2047
Table 35 Digital Audio Interface Clock Output Control



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com