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WM8953ECS/RV 데이터시트(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV 데이터시트(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 100 page ![]() WM8953 Production Data w PD, January 2009, Rev 4.0 18 AUDIO INTERFACE TIMING – SLAVE MODE Figure 4 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns ADCLRC set-up time to BCLK rising edge tLRSU 20 ns ADCLRC hold time from rising edge tLRH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 20 ns Note: BCLK period should always be greater than or equal to MCLK period. |
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