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WM8953ECS/RV 데이터시트(PDF) 79 Page - Wolfson Microelectronics plc

부품명 WM8953ECS/RV
상세설명  Low Power Stereo ADC with PLL and TDM Interface
PDF  100 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8953ECS/RV 데이터시트(HTML) 79 Page - Wolfson Microelectronics plc

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Production Data
WM8953
w
PD, January 2009, Rev 4.0
79
POWER MANAGEMENT
POWER MANAGEMENT REGISTERS
The WM8953 has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To minimise pop or click noise,
it is important to enable or disable functions in the correct order.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4
MICBIAS_ENA
(rw)
0b
MICBIAS Enable
0 = OFF (high impedance output)
1 = ON
2:1
VMID_MODE
[1:0]
(rw)
00b
Vmid Divider Enable and Select
00 = Vmid disabled (for OFF mode)
01 = 2 x 50k
Ω divider (Normal mode)
10 = 2 x 250k
Ω divider (Standby mode)
11 = 2 x 5k
Ω divider (for fast start-up)
R1 (1h)
0
VREF_ENA
(rw)
0b
VREF Enable (Bias for all analogue
functions)
0 = VREF bias disabled
1 = VREF bias enabled
15
PLL_ENA
(rw)
0b
PLL Enable
0 = disabled
1 = enabled
14
TSHUT_ENA
(rw)
0b
Thermal Sensor Enable
0 = Thermal sensor disabled
1 = Thermal sensor enabled
11
OPCLK_ENA
(rw)
0b
GPIO Clock Output Enable
0 = disabled
1 = enabled
9
AINL_ENA
(rw)
0b
Left Input Path Enable
0 = disabled
1 = enabled
8
AINR_ENA
(rw)
0b
Left Input Path Enable
0 = disabled
1 = enabled
7
LIN34_ENA
(rw)
0b
LIN34 Input PGA Enable
0 = disabled
1 = enabled
6
LIN12_ENA
(rw)
0b
LIN12 Input PGA Enable
0 = disabled
1 = enabled
5
RIN34_ENA
(rw)
0b
RIN34 Input PGA Enable
0 = disabled
1 = enabled
4
RIN12_ENA
(rw)
0b
RIN12 Input PGA Enable
0 = disabled
1 = enabled
1
ADCL_ENA
(rw)
0b
Left ADC Enable
0 = disabled
1 = enabled
R2 (02h)
0
ADCR_ENA
(rw)
0b
Right ADC Enable
0 = disabled
1 = enabled
Table 51 Power Management



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