PIC16LC712 datasheet(41/106 Pages) MICROCHIP

41 / 106 page

 1999-2013 Microchip Technology Inc.

DS41106C-page 41

PIC16C712/716

7.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RB3/CCP1 pin is

either:

• driven High

• driven Low

• remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 7-4:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

7.2.1

CCP PIN CONFIGURATION

The user must configure the RB3/CCP1 pin as the CCP

output by clearing the TRISCCP<2> bit.

7.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

7.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

7.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The Special Event Trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The Special Event Trigger output of CCP1 also starts

an A/D conversion (if the A/D module is enabled).

TABLE 7-2:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set flag bit CCP1IF

(PIR1<2>)

match

RB3/CCP1

TRISCCP<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

Reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion

Note:

Clearing the CCP1CON register will force

the RB3/CCP1 compare output latch to

the default low level. This is neither the

PORTB I/O data latch nor the DATACCP

latch.

Note:

The Special Event Trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

Resets

07h

DATACCP

—

DCCP

—DT1CK

xxxx xxxx xxxx xuxu

0Bh,8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

PIR1

—

ADIF

—

CCP1IF

TMR2IF

TMR1IF -0-- -000 -0-- -000

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

10h

T1CON

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

17h

CCP1CON

—

DC1B1

DC1B0

CCP1M3

CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

87h

TRISCCP

—

TCCP

—

TT1CK

xxxx x1x1 xxxx x1x1

8Ch

PIE1

—

ADIE

—

CCP1IE

TMR2IE

TMR1IE -0-- -000 -0-- -000

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.

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