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STM32F051K6 데이터시트(PDF) 78 Page - STMicroelectronics |
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STM32F051K6 데이터시트(HTML) 78 Page - STMicroelectronics |
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78 / 104 page ![]() STM32F051x Electrical characteristics Doc ID 022265 Rev 3 79/105 Figure 22. ADC accuracy characteristics Figure 23. Typical connection diagram using the ADC 1. Refer to Table 54 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. EO EG 1LSBIDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 12 3 4 5 6 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VDDA VSSA 1LSBIDEAL VDDA AINx IL±1 μA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) 12-bit converter CADC(1) Sample and hold ADC converter |
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